Modern integrated circuits (ICs) can easily be damaged by the application of too high a voltage. This may especially result in irreversible damage to gate oxides of metal-oxide-semiconductor (MOS) field-effect transistors in the circuit. Such a high voltage may be transferred to the integrated circuit in particular by an electrostatic discharge (ESD), for example if a person touches terminals of the integrated circuit. Thus it is known to equip integrated circuits with circuit arrangements to protect against ESDs, by which an ESD is diverted to ground, whereby this diversion path is non-conductive in normal operation of the circuit. For this purpose, an appropriately dimensioned negative-channel MOS (NMOS) component is coupled between a terminal of the circuit to be protected and a grounding line, whereby the NMOS component has a blocking behavior during normal operation of the circuit and becomes conductive when an ESD is applied to the terminal.
In the course of the increasing miniaturization of ICs, such as complementary MOS (CMOS) integrated circuits, core supply voltages of circuits (i.e., supply voltages that supply the majority of the circuit) have fallen steadily. By comparison, supply voltages of input/output interfaces (IO interfaces) have remained substantially the same in order to maintain backward compatibility with circuits operated with higher supply voltages.
Such IO interfaces are typically configured such that they can frequently receive signals having a voltage that is even greater than the supply voltage for said IO interfaces or discharge a signal voltage higher than the supply voltage. Such an IO interface is referred to as “over-voltage tolerant IO.”
In some cases, provision is made for different supply voltages in integrated circuits. For example, a chip manufactured in DSM (deep submicron)-CMOS technology, which is usually operated with a supply voltage of 3.3 V, may additionally have a supply voltage terminal for a voltage of 5 V. This may be used to equip the chip with a voltage controller by way of which the chip is supplied with a 5 V voltage supply in an environment where a 3.3 V voltage supply is not available, or to provide appropriate IO interfaces. Such a voltage controller is formed substantially by a single MOS transistor without any problems arising due to degradation of gate oxides since such a MOS transistor, for example a positive-channel MOS (PMOS) transistor, is only connected between the external 5 V supply voltage and the internally generated 3.3 V supply voltage, such that the entire voltage of 5 V does not drop via the transistor, for example between drain and gate, source and gate, or gate and bulk.
Generally, however, a corresponding ESD protective circuit arrangement is connected between the supply voltage, in this case 5 V, and ground. Thus with 3.3 V technology, an ESD protective arrangement based on a single NMOS transistor connected between the supply voltage and ground may suffer from reliability problems since the result might be a degradation of the gate oxide due to the high voltage drop.
It is known, therefore, in such circuits to use two stacked NMOS protective elements so that only a portion of the voltage applied during normal operation of the relevant circuit drops at each protective element.
In such a circuit arrangement, a circuit or circuit section to be protected has a first terminal for a supply voltage and a second terminal for a grounding cable. Between the first terminal and the second terminal are connected two stacked NMOS transistors. Gate terminals of the NMOS transistors are interconnected via resistors to second terminal.
In normal operation of such a circuit, the gate terminals of the NMOS transistors are at ground potential such that the NMOS transistors close and thus no current flows across the NMOS transistors.
Now, if a high voltage is present on the first terminal because of an electrostatic discharge, then the voltage on the gate terminal of one of the NMOS transistors also rises rapidly due to capacitive coupling between the gate terminal of that NMOS transistor and the drain terminal of that NMOS transistor interconnected to the first terminal. By means of further capacitive coupling between the gate terminal of that NMOS transistor and the source terminal of that NMOS transistor (which is interconnected to the drain terminal of the other NMOS transistor) and capacitive coupling between the drain terminal of the other NMOS transistor and the gate terminal of that other NMOS transistor, the voltage at the gate terminal of that other NMOS transistor also increases. At the same time, the resistors have the effect that a voltage other than ground can actually be present at the gate terminals of the NMOS transistors for at least a short time, i.e. during an electrostatic discharge.
The potential effect of this is that the NMOS transistors may become conductive as a breakdown field strength of the NMOS transistors is reached, and thus the electrostatic discharge can drain from the first terminal to ground, i.e. to the second terminal.
Such a circuit may have the disadvantage that the increased voltage at the gate terminals of the NMOS transistors is generally not available for the entire duration of a typical ESD pulse (on the order of magnitude of 150 nanoseconds), which may lead to an increased voltage drop at the NMOS transistors and at the circuit to be protected. Furthermore, such a circuit may not be usable with over-voltage tolerant IO interfaces unless the NMOS transistors are used and that are compatible with the increased supply voltage. This, in turn, however, may incur additional barely acceptable technological investment